Basic Assertions

Aug. 11, 2024 || Item:5.3.Basic Assertions

1. Timing delay

##<delay>: specifies a fixed number of clock cycles or time units to wait before evaluating the next condition or event.

##[min:max]: specifies a range of clock cycles or time units to wait before evaluating the next condition or event. The delay is variable within the specified range.

##[min:$]: same as above, but no upper limitation. 

Example

Output

2. Implication

Until now, assertions have always been checked. In some cases, we only want to check an assertion when certain conditions are met; this is when implication is used.

<antecedent> |-> <consequent>: overlapping implication. If the antecedent sequence is true, then the consequent sequence must start at the same time as the antecedent and must hold true. If antecedent sequence is false, the assertion will be skipped.

<antecedent> |=> <consequent>: non-overlapping implication. If the antecedent sequence is true, then the consequent sequence must start immediately after the antecedent finishes.

 3. Repetition

Repetition is a way to specify that a sequence of events must occur a certain number of times in a row.

@(posedge clk) tb_b |-> ##1 check_c_seq ##1 check_c_seq

same as

@(posedge clk) tb_b |-> ##1 check_c_seq[*2]

Example 1 (overlap)

Output 

Example 2 (non-overlap)

Output 

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