-
System Verilog
1.Data types
-
1.1.Integer, Real, Void
1.2.Comming soon...
1.3.String
1.4.Paremeter and User-defined
1.5.Enumerations
1.6.Structures and Unions
1.7.Class
1.8.Singular and Aggregate types
1.9.Casting
-
2.1.Packed and Unpacked arrays
2.2.Multi dimensions
2.3.Indexing, slicing and querying functions of arrays
2.4.Dynamic arrays
2.5.Array assignment
2.6.Arrays as argument
2.7.Associative arrays
2.8.Associative array methods, assignment, arguments, literals
2.D.Queues
2.E.Array manipulation methods
Concurrent Assertions
Jan. 20, 2024 || Item:5.2.Concurrent AssertionsConcurrent assertions are evaluated over multiple clock cycles and are used to monitor sequences of events over time. It's only evaluated on clock edge.
A concurrent assertion is often created using Sequence and Property.
Sequence: define a series of events or conditions that occur over time, which is essential for expressing temporal relationships in hardware designs.
Property: use sequences to specify conditions or behaviors that must hold true. The property can then be used in assertions to check if the design behaves as expected over multiple clock cycles.
We can define a clock in a sequence. However, it's recommended that the clock be defined in a property to increase the reusability of the basic sequence.
Example
Output
