SystemVerilog offers several Integer data types, representing a hybrid of both Verilog and C data types.
It use integer arithmetic and can be signed or unsigned. This affects the meaning of certain operators such as ‘<’, etc.
2-state: 0 or 1
Default value: 0
longint/int/shortint: 64 / 32 / 16-bit signed integer
byte: 8-bit signed integer or ASCII character
bit: user-defined vector size
4-state: 0, 1, x(unknown) and z(impedance)
Default value: x
logic/reg: user-defined vector size
integer: 32-bit signed integer
time: 64-bit unsigned integer
Note that the signed keyword is part of Verilog-2001. The unsigned keyword is a reserved keyword in Verilog-2001, but is not utilized.
The real data type, same as C double, represents a 64-bit floating-point number with high precision, suitable for simulating analog circuits or complex mathematical operations. Its range spans from approximately -1.7976931348623157E+308 to 1.7976931348623157E+308, with about 15 digits of precision.
The shortreal data type, same as C float, represents a 32-bit floating-point number, often utilized in digital design verification for quicker simulation and reduced memory consumption. Its value range extends from about -3.40282347E+38 to 3.40282347E+38, with around 7 digits of precision.
The void data type represents non-existent data. This type can be specified as the return type of functions, indicating no return value. This type can also be used for members of tagged unions.