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System Verilog
1.Data types
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1.1.Integer, Real, Void
1.2.Comming soon...
1.3.String
1.4.Paremeter and User-defined
1.5.Enumerations
1.6.Structures and Unions
1.7.Class
1.8.Singular and Aggregate types
1.9.Casting
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2.1.Packed and Unpacked arrays
2.2.Multi dimensions
2.3.Indexing, slicing and querying functions of arrays
2.4.Dynamic arrays
2.5.Array assignment
2.6.Arrays as argument
2.7.Associative arrays
2.8.Associative array methods, assignment, arguments, literals
2.D.Queues
2.E.Array manipulation methods
Immediate Assertion
Jan. 20, 2024 || Item:5.1.Immediate AssertionSystemVerilog assertions (SVA) are used to check if a design behaves as expected. Assertions express design properties or conditions that must hold true at certain times during the execution of the hardware. They help detect and diagnose functional errors early in the design cycle.
In SystemVerilog there are two main kinds of assertions: immediate and concurrent.
Immediate Assertion
Immediate asertions are evaluated as soon as the statement is executed, typically used for conditions that should hold true in a single simulation cycle.
Syntax:
label: assert(expression) pass_statement; else fail_statement;
Where:
label (identifier and colon): optional, creates a named block around the assertion statement
pass_statement, fail_statement:optional, depending on the value of the expression, either pass_statement or fail_statement will be executed.
There are three severity system tasks that can be included in the fail statement to specify a severity level: $fatal, $error (the default severity) and $warning. In addition, the system task $info indicates that the assertion failure carries no specific severity.
If the pass_statement and fail_statement are not specified, a assertion error report will be generated.
Example:
Output:
