In SystemVerilog Assertions (SVA), Sequences, Boolean expressions, and Properties are related constructs used to describe and specify conditions within a hardware design.
1. Boolean expressions
A boolean expression is a logical condition that evaluates to either TRUE or FALSE, same way as an expression is interpreted in the condition of a procedural if statement.
In the context of assertions, boolean expressions are often used within sequence or properties to define conditions that must hold true during simulation or formal verification.
The sequence feature provides the capability to build and manipulate sequential behaviors. The simplest sequential behaviors are linear. A linear sequence is a finite list of SystemVerilog boolean expressions in a linear order of increasing time.
More complex sequential behaviors are described by SystemVerilog sequences. A sequence is a regular expression over the SystemVerilog boolean expressions that concisely specifies a set of zero, finitely many, or infinitely many linear sequences.
Syntax:
sequence name_of_sequence;
……
endsequence
3. Property
A property is a higher-level construct that combines sequences and boolean expressions to express more complex conditions or requirements.
Properties are used to specify the desired behavior or properties of a hardware design.
Syntax:
property name_of_property;
<expression or complex sequence expressions>
endproperty